A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
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IEEE J. Solid State Circuits, 2019
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm<sup>2</sup>and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
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Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
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Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
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IEEE J. Solid State Circuits, 2017
A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
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IEEE J. Solid State Circuits, 2017
Design of nonvolatile processors and applications.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
A compare-and-select error tolerant scheme for nonvolatile processors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
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Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Multistage Function Speculation Adders.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Design exploration of inrush current aware controller for nonvolatile processor.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
An energy-efficient heterogeneous dual-core processor for Internet of Things.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015