An Area-Efficient Accelerator for Non-Maximum Suppression.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
A 40nm area-efficient Effective-bit-combination-based DNN accelerator with the reconfigurable multiplier.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
LG-LSQ: Learned Gradient Linear Symmetric Quantization for Low-Precision Integer Hardware.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
LG-LSQ: Learned Gradient Linear Symmetric Quantization.
CoRR, 2022
A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 104.76-TOPS/W, Spike-Based Convolutional Neural Network Accelerator with Reduced On-Chip Memory Data Flow and Operation Unit Skipping.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 62.45 TOPS/W Spike-Based Convolution Neural Network Accelerator with Spatiotemporal Parallel Data Flow and Sparsity Mechanism.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
MARSv2: Multicore and Programmable Reconstruction Architecture SRAM CIM-Based Accelerator with Lightweight Network.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
A Landscape of Cryptocurrencies.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019