Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Hardware-efficient parallel FIR digital filter structures for symmetric convolutions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems.
IEEE J. Solid State Circuits, 2008