The Design and Implementation of a Highly Efficient and Low-Complexity Joint-MMSE GFDM Receiver.
J. Signal Process. Syst., 2021
Design of 2D Systolic Array Accelerator for Quantized Convolutional Neural Networks.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems.
Circuits Syst. Signal Process., 2020