37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.
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Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
Research progress on low-power artificial intelligence of things (AIoT) chip design.
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Sci. China Inf. Sci., October, 2023
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.
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Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023