2025
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
APCPU: Adaptive-Pooling Compression Processing Unit for Energy-Efficient DNNs Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
CPSnB: Compressing and Processing Spatial Similarity near Memory Bank for DNNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Digital Predistortion for Quadrature Digital Power Amplifiers Using Deep Neural Network of AT_LSTM: Attention LSTM.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation.
IEEE Access, 2023
2022
Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM.
IEEE Trans. Computers, 2017
3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.
Microelectron. J., 2017
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A self-adaptive write driver with fast termination of step-up pulse for ReRAM.
IEICE Electron. Express, 2016
Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A low cost and high reliability true random number generator based on resistive random access memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
,
,
,
,
,
,
,
,
,
,
IEEE J. Solid State Circuits, 2013
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage.
IEICE Electron. Express, 2012
Variation-tolerant Cu<sub>x</sub>Si<sub>y</sub>O-based RRAM for low power application.
IEICE Electron. Express, 2012
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction.
,
,
,
,
,
,
,
,
,
,
Proceedings of the Symposium on VLSI Circuits, 2012
2011
Novel 2T programmable element to improve density and performance of FPGA.
IEICE Electron. Express, 2011
A BIST scheme for high-speed Gain Cell eDRAM.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Novel RRAM programming technology for instant-on and high-security FPGAs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell.
IEICE Trans. Electron., 2010
2007
Multilevel Storage in Phase-Change Memory.
IEICE Trans. Electron., 2007
2006
Electronic properties of GST for non-volatile memory.
Microelectron. J., 2006
Characterization of Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> thin film transistor and its application in non-volatile memory.
Microelectron. J., 2006