An Energy-Efficient Capacitive-RRAM Content Addressable Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications.
Microelectron. J., 2024
An Energy-efficient Capacitive-Memristive Content Addressable Memory.
CoRR, 2024
Coherent point drift with Skewed Distribution for accurate point cloud registration.
Comput. Graph., 2024
Multi-State Memristors and Their Applications: An Overview.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A CMOS-based Characterisation Platform for Emerging RRAM Technologies.
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Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
High-Density Digital RRAM-based Memory with Bit-line Compute Capability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.
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IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.
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IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A High-Fidelity, Machine-Learning Enhanced Queueing Network Simulation Model For Hospital Ultrasound Operations.
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Proceedings of the Winter Simulation Conference, 2021
A RRAM-Based Associative Memory Cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Hybrid CMOS/Memristor Circuit Design Methodology.
CoRR, 2020
2nd Place Solution to ECCV 2020 VIPriors Object Detection Challenge.
CoRR, 2020
A Cluster-Based Neuromorphic ISFET Architecture with Integrated Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020