Quality-driven design of deep neural network hardware accelerators for low power CPS and IoT applications.
Microprocess. Microsystems, 2024
Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding.
Microprocess. Microsystems, 2014
Design of massively parallel hardware multi-processors for highly-demanding embedded applications.
Microprocess. Microsystems, 2013
Hardware Multi-processor Design for Highly-Demanding Applications.
Proceedings of the Tenth International Conference on Information Technology: New Generations, 2013
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.
VLSI Design, 2012
Scalable communication architectures for massively parallel hardware multi-processors.
J. Parallel Distributed Comput., 2012
Architecture Design of Reconfigurable Accelerators for Demanding Applications.
Proceedings of the Seventh International Conference on Information Technology: New Generations, 2010
Quality-driven methodology for demanding accelerator design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.
Proceedings of the Embedded Computer Systems: Architectures, 2009
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.
Proceedings of the Reconfigurable Computing: Architectures, 2009