OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.
CoRR, 2024
SenseDSE: Sensitivity-Based Performance Evaluation for Design Space Exploration of Microarchitecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
TPNoC: An Efficient Topology Reconfigurable NoC Generator.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Graph Representation Learning for Microarchitecture Design Space Exploration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
An Automated Compiler for RISC-V Based DNN Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022