Finite mixtures of matrix variate Poisson-log normal distributions for three-way count data.
Bioinform., May, 2023
Directed Test Generation for Validation of Cache Coherence Protocols.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Learning-oriented Property Decomposition for Automated Generation of Directed Tests.
J. Electron. Test., 2014
TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Scalable Test Generation by Interleaving Concrete and Symbolic Execution.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Energy-Aware Scheduling and Dynamic Reconfiguration in Real-Time Systems.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012
Directed test generation for validation of multicore architectures.
ACM Trans. Design Autom. Electr. Syst., 2012
TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Automated generation of directed tests for transition coverage in cache coherence protocols.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Decoding-Aware Compression of FPGA Bitstreams.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Efficient directed test generation for validation of multicore architectures.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Synchronized Generation of Directed Tests Using Satisfiability Solving.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Efficient decision ordering techniques for SAT-based test generation.
Proceedings of the Design, Automation and Test in Europe, 2010
A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Efficient Placement of Compressed Code for Parallel Decompression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Object Extraction by Spatio-Temporal Assembling.
Proceedings of the International Conference on Image Processing, 2007