A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.
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IEEE J. Solid State Circuits, March, 2024
A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion.
IEEE J. Solid State Circuits, September, 2023
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.
IEEE J. Solid State Circuits, September, 2023
An In-Memory-Computing Charge-Domain Ternary CNN Classifier.
IEEE J. Solid State Circuits, May, 2023
LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
A Multi-Day Wearable Surface EMG E-Tattoo for Fatigue Monitoring.
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS.
IEEE J. Solid State Circuits, 2021
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.
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IEEE J. Solid State Circuits, 2020
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.
IEEE J. Solid State Circuits, 2020
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.
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IEEE J. Solid State Circuits, 2020
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019