2025
Global Placement Exploiting Soft 2D Regularity.
ACM Trans. Design Autom. Electr. Syst., March, 2025
2024
Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement.
Proceedings of the 2024 International Symposium on Physical Design, 2024
HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical Designs.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
2023
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.
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ACM Trans. Reconfigurable Technol. Syst., December, 2023
The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023
Systolic Array Placement on FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2020
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
High-Definition Routing Congestion Prediction for Large-Scale FPGAs.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A New Paradigm for FPGA Placement Without Explicit Packing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2019
Simultaneous Placement and Clock Tree Construction for Modern FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.
ACM Trans. Design Autom. Electr. Syst., 2018
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
Placement mitigation techniques for power grid electromigration.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
2014
Live demonstration: An optimization software and a design case of a novel dual band wireless power and data transmission system.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014