A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON.

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS.

25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS.

A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS.

A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET.

A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS.

A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS.

A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS.

A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS.

A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications.

An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC.

Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver.

A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer.

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.

A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET.

An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology.

An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation.

Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs.

Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop.

A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.

An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor.

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor.

A 108fs_rms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching.

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery.

PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer.

A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier.

A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis.

A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis.

SSC tracking analysis and a deeper-SSC estimator.

A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL.

A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning.

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.

Design Consideration of 6.25 Gbps Signaling for High-Performance Server.