2023
A Research Retrospective on AMD's Exascale Computing Journey.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2019
Understanding the Impact of Socket Density in Density Optimized Servers.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.
CoRR, 2018
2017
Ti-States: Power Management in Active Timing Margin Processors.
IEEE Micro, 2017
Design and Analysis of an APU for Exascale Computing.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Dynamic GPGPU Power Management Using Adaptive Model Predictive Control.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
A framework for evaluating promising power efficiency techniques in future GPUs for HPC.
Proceedings of the 24th High Performance Computing Symposium, 2016
Ti-states: Processor power management in the temperature inversion region.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Measuring and modeling on-chip interconnect power on real hardware.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
Performance Boosting Opportunities under Communication Imbalance in Power-Constrained HPC Clusters.
Proceedings of the 45th International Conference on Parallel Processing, 2016
A Case for Criticality Models in Exascale Systems.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016
2015
Harmonia: balancing compute and memory power in high-performance GPUs.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
A Taxonomy of GPGPU Performance Scaling.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015
2014
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
2013
Architectural implications of spatial thermal filtering.
Integr., 2013
2012
Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall.
IEEE Trans. Computers, 2012
Accurate Fine-Grained Processor Power Proxies.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Power-efficient time-sensitive mapping in heterogeneous systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Scaling with Design Constraints: Predicting the Future of Big Chips.
IEEE Micro, 2011
Temperature-Aware Architecture: Lessons and Opportunities.
IEEE Micro, 2011
Power shifting in Thrifty Interconnection Network.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
TAPO: Thermal-aware power optimization techniques for servers and data centers.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011
2010
Temperature-to-power mapping.
Proceedings of the 28th International Conference on Computer Design, 2010
2009
Differentiating the roles of IR measurement and simulation for power and temperature-aware design.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009
2008
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model.
IEEE Trans. Computers, 2008
Many-core design from a thermal perspective.
Proceedings of the 45th Design Automation Conference, 2008
2007
Interconnect Lifetime Prediction for Reliability-Aware Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2007
2006
HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design.
IEEE Trans. Very Large Scale Integr. Syst., 2006
A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
2005
The need for a full-chip and package thermal model for thermally optimized IC designs.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Monitoring Temperature in FPGA based SoCs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Analytical Model for Sensor Placement on Microprocessors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2004
Temperature-aware microarchitecture: Modeling and implementation.
ACM Trans. Archit. Code Optim., 2004
Interconnect lifetime prediction under dynamic stress for reliability-aware design.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Compact thermal modeling for temperature-aware design.
Proceedings of the 41th Design Automation Conference, 2004
2003
HotSpot: a dynamic compact thermal model at the processor-architecture level.
Microelectron. J., 2003
Temperature-Aware Computer Systems: Opportunities and Challenges.
IEEE Micro, 2003
Temperature-Aware Microarchitecture.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003