2023

Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology.

[DOI]

C. A. Lu

,

H. P. Lee

,

H. C. Chen

,

Y. C. Lin

,

Y. H. Chung

,

S. H. Wang

,

J. Y. Yeh

,

V. S. Chang

,

M. C. Chiang

,

W. Chang

,

H. C. Chung

,

C. F. Cheng

,

H. H. Hsu

,

H. H. Liu

,

William P. N. Chen

,

C. Y. Lin

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023