Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices.
Proceedings of the International Symposium on Memory Systems, 2024
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications.
IEEE Micro, 2022
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars.
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Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
The N3XT Approach to Energy-Efficient Abundant-Data Computing.
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Proc. IEEE, 2019
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
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Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
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IEEE J. Solid State Circuits, 2018
Hyperdimensional Computing Nanosystem.
CoRR, 2018
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Resistive RAM-Centric Computing: Design and Modeling Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
3D nanosystems enable <i>embedded</i> abundant-data computing: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Nano-engineered architectures for ultra-low power wireless body sensor nodes.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Monolithic 3D integration: a path from concept to reality.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015