2024
A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes.
Sensors, May, 2024
Hardware Schemes for Smarter Indoor Robotics to Prevent the Backing Crash Framework Using Field Programmable Gate Array-Based Multi-Robots.
Sensors, March, 2024
Hierarchical Object-Aware Dual-Level Contrastive Learning for Domain Generalized Stereo Matching.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2024, 2024
Achieving Real-time Visual Tracking with Low-Cost Edge AI.
Proceedings of the 15th ACM/IEEE International Conference on Cyber-Physical Systems, 2024
GPSFormer: A Global Perception and Local Structure Fitting-Based Transformer for Point Cloud Understanding.
Proceedings of the Computer Vision - ECCV 2024, 2024
2023
A Versatile Approach to Polygonal Object Avoidance in Indoor Environments with Hardware Schemes Using an FPGA-Based Multi-Robot.
Sensors, December, 2023
DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
2022
Reconfiguration algorithms for synchronous communication on switch based degradable arrays.
Parallel Comput., 2022
Traffic Speed Prediction of Road Cluster with Heterogeneous Sampling Frequency.
Proceedings of the 13th IEEE International Symposium on Parallel Architectures, 2022
2021
Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors.
IEEE Trans. Computers, 2021
Road-network aware Dynamic Workload Balancing Technique for Real-time Route Generation in On-Demand Public Transit.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021
Incorporating Compiler Optimization in Software Estimation for FPGA-based Embedded Processors.
Proceedings of the 4th International Conference on Information and Computer Technologies, 2021
2020
Rapid and Robust Background Modeling Technique for Low-Cost Road Traffic Surveillance Systems.
IEEE Trans. Intell. Transp. Syst., 2020
Hardware Performance Counter-Based Fine-Grained Malware Detection.
ACM Trans. Embed. Comput. Syst., 2020
LAMBDA: Lightweight Assessment of Malware for emBeddeD Architectures.
ACM Trans. Embed. Comput. Syst., 2020
Improving accuracy of HPC-based malware classification for embedded platforms using gradient descent optimization.
J. Cryptogr. Eng., 2020
Blockchain-based public auditing for big data in cloud storage.
Inf. Process. Manag., 2020
HARDY: Hardware based Analysis for malwaRe Detection in embedded sYstems.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Accelerating Computer Vision Algorithms on Heterogeneous Edge Computing Platforms.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Evaluating the Merits of Ranking in Structured Network Pruning.
Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020
Technique for Vendor and Device Agnostic Hardware Area-Time Estimation.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
Fast Computation of Clustered Many-to-many Shortest Paths and Its Application to Map Matching.
ACM Trans. Spatial Algorithms Syst., 2019
Rapid Technique to Eliminate Moving Shadows for Accurate Vehicle Detection.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2019
Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Cluster-First, Route-Second Heuristic for EV Scheduling in On-Demand Public Transit.
Proceedings of the 2019 IEEE International Conference on Cybernetics and Intelligent Systems (CIS) and IEEE Conference on Robotics, 2019
Genetic Algorithm based Dynamic Scheduling of EV in a Demand Responsive Bus Service for First Mile Transit.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019
Towards Scalable Lifetime Reliability Management for Dark Silicon Manycore Systems.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
An Iterative Technique for Runtime Efficient Hardware-Software Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Dependency-Aware Clustering for Variable-Grained Hardware-Software Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Genetic Algorithm based EV Scheduling for On-Demand Public Transit System.
Proceedings of the Computational Science - ICCS 2019, 2019
LifeGuard: A Reinforcement Learning-Based Task Mapping Strategy for Performance-Centric Aging Management.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Framework for Rapid Performance Estimation of Embedded Soft Core Processors.
ACM Trans. Reconfigurable Technol. Syst., 2018
Vision-based patient monitoring: a comprehensive review of algorithms and technologies.
J. Ambient Intell. Humaniz. Comput., 2018
Algorithms for Replica Placement and Update in Tree Network.
Comput. J., 2018
Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
A Simulation Framework for a Real-Time Demand Responsive Public Transit System.
Proceedings of the 21st International Conference on Intelligent Transportation Systems, 2018
Communication-Aware Module Placement for Power Reduction in Large FPGA Designs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Hybrid Genetic Algorithm for an On-Demand First Mile Transit System Using Electric Vehicles.
Proceedings of the Computational Science - ICCS 2018, 2018
A Hybrid Methodology for Optimal Fleet Management in an Electric Vehicle Based Flexible Bus Service.
Proceedings of the 15th International Conference on Control, 2018
Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-Software Partitioning in FPGA-based SoCs for IoT Applications.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018
Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software Partitioning in FPGA-Based SoCs for IoT Devices.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Side-Channel Assisted Malware Classifier with Gradient Descent Correction for Embedded Platforms.
Proceedings of the PROOFS 2018, 2018
LifeSim: A lifetime reliability simulator for manycore systems.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018
Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
A Framework for Fast and Robust Visual Odometry.
IEEE Trans. Intell. Transp. Syst., 2017
Online Map-Matching of Noisy and Sparse Location Data With Hidden Markov and Route Choice Models.
IEEE Trans. Intell. Transp. Syst., 2017
Low complexity techniques for robust real-time traffic incident detection.
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017
Fault-Driven Reconfiguration Algorithm for Processor Arrays.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017
High Speed Performance Estimation of Embedded Hard-core Processors in FPGA-based SoCs.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
Communication-aware Partitioning for Energy Optimization of Large FPGA Designs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Low-Complexity Global Motion Estimation for Aerial Vehicles.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2017
Low-Complexity Signature-Based Malware Detection for IoT Devices.
Proceedings of the Applications and Techniques in Information Security, 2017
2016
Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Enhanced low-complexity pruning for corner detection.
J. Real Time Image Process., 2016
Algorithms for bi-objective multiple-choice hardware/software partitioning.
Comput. Electr. Eng., 2016
Real-time road traffic density estimation using block variance.
Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision, 2016
Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016
Robust and low complexity obstacle detection and tracking.
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016
Heuristic optimizations for high-speed low-latency online map matching with probabilistic sequence models.
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices.
Proceedings of the International Symposium on Integrated Circuits, 2016
Reducing Access Latency in Virtual Machine Assignments.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016
Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Rapid design space exploration for soft core processor customization and selection.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
2015
Algorithmic aspects of graph reduction for hardware/software partitioning.
J. Supercomput., 2015
Nonparametric Technique Based High-Speed Road Surface Detection.
IEEE Trans. Intell. Transp. Syst., 2015
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Adaptive Window Strategy for High-Speed and Robust KLT Feature Tracker.
Proceedings of the Image and Video Technology - 7th Pacific-Rim Symposium, 2015
Probabilistic Map Matching of Sparse and Noisy Smartphone Location Data.
Proceedings of the IEEE 18th International Conference on Intelligent Transportation Systems, 2015
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Identifying epileptic seizures based on a template-based eyeball detection technique.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015
Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Rapid estimation of DSPs utilization for efficient high-level synthesis.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Compute-efficient eye state detection: algorithm, dataset and evaluations.
Proceedings of the 9th International Conference on Distributed Smart Camera, 2015
Fast Replica Placement and Update Strategies in Tree Networks.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015
2014
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2014
Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays.
IEEE Trans. Parallel Distributed Syst., 2014
Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective.
ACM Trans. Design Autom. Electr. Syst., 2014
Parallel reconfiguration algorithms for mesh-connected processor arrays.
J. Supercomput., 2014
Rapid evaluation of custom instruction selection approaches with FPGA estimation.
ACM Trans. Embed. Comput. Syst., 2014
Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control.
J. Low Power Electron., 2014
Constructing Low-temperature sub-Arrays on Reconfigurable VLSI Arrays.
J. Circuits Syst. Comput., 2014
Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs.
J. Circuits Syst. Comput., 2014
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis.
Int. J. Reconfigurable Comput., 2014
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance.
Int. J. Reconfigurable Comput., 2014
Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014
Algorithmic Aspects for Bi-Objective Multiple-Choice Hardware/Software Partitioning.
Proceedings of the Sixth International Symposium on Parallel Architectures, 2014
Stereo based ROIs generation for detecting pedestrians in close proximity.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014
Robust real-time route inference from sparse vehicle position data.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014
Vision-based pedestrian tracking system using color and motion cue.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Reducing computational complexity for face detection.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Mask-based non-maximal suppression with iterative pruning for low-complexity corner detection.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A Compute-Efficient Algorithm for Robust Eyebrow Detection.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Soft error mitigation through selection of noninvert implication paths.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
Automated thresholding for low-complexity corner detection.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
Efficient heuristic and tabu search for hardware/software partitioning.
J. Supercomput., 2013
Perceptual Full-Reference Quality Assessment of Stereoscopic Images by Considering Binocular Visual Characteristics.
IEEE Trans. Image Process., 2013
FPGA-aware techniques for rapid generation of profitable custom instructions.
Microprocess. Microsystems, 2013
Iris Recognition Using Stable Dark Features.
J. Comput., 2013
CADSE: communication aware design space exploration for efficient run-time MPSoC management.
Frontiers Comput. Sci., 2013
Block-Based Search Space Reduction Technique for Face Detection Using Shoulder and Head Curves.
Proceedings of the Image and Video Technology - 6th Pacific-Rim Symposium, 2013
Additive Hough Transform on embedded computing platforms.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Identifying lane types: A modular approach.
Proceedings of the 16th International IEEE Conference on Intelligent Transportation Systems, 2013
Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Modelling communication overhead for accessing local memories in hardware accelerators.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2012
Psychoacoustic Model Compensation for Robust Speaker Verification in Environmental Noise.
IEEE Trans. Speech Audio Process., 2012
Iris Recognition of Defocused Images for Mobile phones.
Int. J. Pattern Recognit. Artif. Intell., 2012
Algorithmic aspects for multiple-choice hardware/software partitioning.
Comput. Oper. Res., 2012
Robust extraction of lane markings using gradient angle histograms and directional signed edges.
Proceedings of the 2012 IEEE Intelligent Vehicles Symposium, 2012
Detection & classification of arrow markings on roads using signed edge signatures.
Proceedings of the 2012 IEEE Intelligent Vehicles Symposium, 2012
Low-complexity pruning for accelerating corner detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Exploiting stable features for iris recognition of defocused images.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Reconfiguration Algorithms for Degradable VLSI Arrays with Switch Faults.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Area-time estimation of C-based functions for design space exploration.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Dataflow graph partitioning for high level synthesis.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Custom instructions with local memory elements without expensive DMA transfers.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
2011
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms.
ACM Trans. Design Autom. Electr. Syst., 2011
A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM.
Trans. High Perform. Embed. Archit. Compil., 2011
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs.
IEEE Trans. Computers, 2011
Algorithm for Time-dependent Shortest Safe Path on Transportation Networks.
Proceedings of the International Conference on Computational Science, 2011
Field programmable gate array-based acceleration of shortest-path computation.
IET Comput. Digit. Tech., 2011
Accelerating identification of custom instructions for extensible processors.
IET Circuits Devices Syst., 2011
Instruction set customization for area-constrained FPGA designs.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Computation and communication aware run-time mapping for NoC-based MPSoC platforms.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Compiler-assisted technique for rapid performance estimation of FPGA-based processors.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011
Utilizing Dark Features for Iris Recognition in Less Constrained Environments.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011
Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011
Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
A Design Space Exploration Methodology for Application Specific MPSoC Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
A Low-Complexity Speaker-and-Word Recognition Application for Resource-Constrained Devices.
Proceedings of the International Symposium on Electronic System Design, 2011
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs.
Proceedings of the 14th International Conference on Compilers, 2011
2010
Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms.
IEEE Trans. Computers, 2010
Run-time mapping of multiple communicating tasks on MPSoC platforms.
Proceedings of the International Conference on Computational Science, 2010
Efficient heuristic algorithms for path-based hardware/software partitioning.
Math. Comput. Model., 2010
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms.
J. Syst. Archit., 2010
Selecting profitable custom instructions for reconfigurable processors.
J. Syst. Archit., 2010
Instruction cache tuning for embedded multitasking applications.
IET Comput. Digit. Tech., 2010
Hierarchical Additive Hough Transform for Lane Detection.
IEEE Embed. Syst. Lett., 2010
Rapid Techniques for Performance Estimation of Processors.
J. Res. Pract. Inf. Technol., 2010
A Novel Approach for Multilevel Fixed Outline Floorplanning.
Proceedings of the Third International Symposium on Parallel Architectures, 2010
An efficient edge and corner detector.
Proceedings of the 11th International Conference on Control, 2010
Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2010
Performance estimation framework for FPGA-based processors.
Proceedings of the International Conference on Field-Programmable Technology, 2010
Accelerating shortest path computations in hardware.
Proceedings of the IEEE Conference on Automation Science and Engineering, 2010
Architecture-Aware Custom Instruction Generation for Reconfigurable Processors.
Proceedings of the Reconfigurable Computing: Architectures, 2010
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations.
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Exploiting Inherent Parallelisms for Accelerating Linear Hough Transform.
IEEE Trans. Image Process., 2009
Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures.
IEEE Trans. Ind. Electron., 2009
Rapid design of area-efficient custom instructions for reconfigurable embedded processing.
J. Syst. Archit., 2009
Run-time management of custom instructions on a partially reconfigurable architecture.
Int. J. Inf. Commun. Technol., 2009
Minimizing interconnect length on reconfigurable meshes.
Frontiers Comput. Sci. China, 2009
Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Techniques for Area-time Efficient Image Rotation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Modeling RTOS Components for Instruction Cache Hit Rate Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Gradient angle histograms for efficient linear Hough transform.
Proceedings of the International Conference on Image Processing, 2009
Rapid design exploration framework for application-aware customization of soft core processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
A Parallel Paths Communication Technique for Energy Efficient Wireless Sensor Networks.
Proceedings of the Ad Hoc Networks, First International Conference, 2009
Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection.
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009
Efficient Approximate Algorithm for Hardware/Software Partitioning.
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009
A Hybrid Branch-and-Bound Strategy for Hardware/Software Partitioning.
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009
2008
Parallelizing the Hough Transform Computation.
IEEE Signal Process. Lett., 2008
Algorithmic aspects for power-efficient hardware/software partitioning.
Math. Comput. Simul., 2008
New Model and Algorithm for Hardware/Software Partitioning.
J. Comput. Sci. Technol., 2008
Compiler Back End Design for Translating Multi-radio Descriptions to Operating System-less Asynchronous Processor Datapaths.
J. Comput., 2008
Energy-efficient cluster-based scheme for failure management in sensor networks.
IET Commun., 2008
Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design.
Des. Autom. Embed. Syst., 2008
A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008
Finding minimum interconnect sub-arrays in reconfigurable VLSI arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Performance Estimation: IPC.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008
A Short Course on Implementing FPGA Based Digital Systems.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
Rapid estimation of instruction cache hit rates using loop profiling.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
A Residue-to-Binary Converter for a New Five-Moduli Set.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches.
IEEE Trans. Computers, 2007
Rapid Area-Time Estimation Technique for Porting C-based Applications onto FPGA platforms.
Scalable Comput. Pract. Exp., 2007
Size-restricted cluster formation and cluster maintenance technique for mobile ad hoc networks.
Int. J. Netw. Manag., 2007
One-dimensional Search Algorithms for Hardware/Software Partitioning.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007
A Cluster-Based Approach to Fault Detection and Recovery in Wireless Sensor Networks.
Proceedings of the 4th IEEE International Symposium on Wireless Communication Systems, 2007
An Embedded Systems graduate education for Singapore.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007
Real Time Tracking of Camera Motion Through Cylindrical Passages.
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Unified Cordic Based Processor for Image Processing.
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Improved Spectral Subtraction Technique for Text-Independent Speaker Verification.
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Reconfigurable Frame Parser Design for Multi-Radio Support on Asynchronous Microprocessor Cores.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Algorithmic aspects of area-efficient hardware/software partitioning.
J. Supercomput., 2006
Scalable and modular memory-based systolic architectures for discrete Hartley transform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches.
IEEE Trans. Computers, 2006
Rapid generation of custom instructions using predefined dataflow structures.
Microprocess. Microsystems, 2006
An efficient algorithm for the collapsing knapsack problem.
Inf. Sci., 2006
Low-complex dynamic programming algorithm for hardware/software partitioning.
Inf. Process. Lett., 2006
Efficient Architectures for Segmentation of Endoscopic Images in Micro-Robotic Auto Navigation Systems.
Int. J. Humanoid Robotics, 2006
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006
FPGA based DPA-resistant Unified Architecture for Signcryption.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006
Profile Directed Instruction Cache Tuning for Embedded Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Low Area-time Complexity Averaging Scheme for Thumbnail Generation.
Proceedings of the Ninth International Conference on Control, 2006
Efficient management of custom instructions for run-time reconfigurable instruction set processors.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
Efficient algorithm for functional scheduling in hardware/software co-design.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
Energy Efficient Cache Tuning with Performance Bound.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Design considerations for multi-radio co-existence on asynchronous processors using LAD extensions.
Proceedings of the 40th Annual Conference on Information Sciences and Systems, 2006
Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
An Efficient Algorithm for DPA-resistent RSA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
New Reconfiguration Algorithm for Degradable VLSI Arrays.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware Area.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Efficient reconfigurable techniques for VLSI arrays with 6-port switches.
IEEE Trans. Very Large Scale Integr. Syst., 2005
New adaptive color quantization method based on self-organizing maps.
IEEE Trans. Neural Networks, 2005
VLSI-efficient schemes for high-speed construction of tangent graph.
Robotics Auton. Syst., 2005
Power Efficient Sub-Array in Reconfigurable VLSI Meshes.
J. Comput. Sci. Technol., 2005
Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Practical Techniques for Performance Estimation of Processors.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
DASCA: A Degree and Size based Clustering Approach for Wireless Sensor Networks.
Proceedings of the 2nd IEEE International Symposium on Wireless Communication Systems, 2005
Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Elimination of sign precomputation in flat CORDIC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A configurable dual moduli multi-operand modulo adder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A new design method to modulo 2<sup>n</sup>-1 squaring.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A new formulation of fast diminished-one multioperand modulo 2<sup>n</sup>/+1 adder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Efficient Techniques and Hardware Analysis for Mesh-Connected Processors.
Proceedings of the Distributed and Parallel Computing, 2005
Morphable Structures for Reconfigurable Instruction Set Processors.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
Minimizing Power in Hardware/Software Partitioning.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction.
IEEE Trans. Ind. Electron., 2004
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System.
IEEE Trans. Computers, 2004
An efficient data structure for branch-and-bound algorithm.
Inf. Sci., 2004
Knapsack Model and Algorithm for Hardware/Software Partitioning Problem.
Comput. Artif. Intell., 2004
A novel distributed cluster maintenance technique for high mobility ad-hoc networks.
Proceedings of the 1st IEEE International Symposium on Wireless Communication Systems, 2004
Fast reconfiguring mesh-connected VLSI arrays.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Design of residue-to-binary converter for a new 5-moduli superset residue number system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
High-throughput image rotation using sign-prediction based redundant cordic algorithm.
Proceedings of the 2004 International Conference on Image Processing, 2004
Knapsack Model and Algorithm for HW/SW Partitioning Problem.
Proceedings of the Computational Science, 2004
RTOS acceleration on soft-core processors using instruction set customization.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
2003
A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation.
J. Syst. Archit., 2003
An improved reconfiguration algorithm for degradable VLSI/WSI arrays.
J. Syst. Archit., 2003
A Run-time Reconfiguration Algorithm for VLSI Arrays.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Implementing Otsu's thresholding process using area-time efficient logarithmic approximation unit.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Architectural design and analysis toolbox to implement shortest path algorithms in hardware.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Low cost logarithmic techniques for high-precision computations.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Partial rerouting algorithm for reconfigurable VLSI arrays.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Design of a high speed reverse converter for a new 4-moduli set residue number system.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
New efficient residue-to-binary converters for 4-moduli set {2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1, 2<sup>n+1</sup> - 1}.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays.
Proceedings of the Computational Science - ICCS 2003, 2003
Vector quantization techniques for GMM based speaker verification.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
An adaptive initialization technique for color quantization by self organizing feature map.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design.
Proceedings of the International Conference on Embedded Systems and Applications, 2003
Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform.
Proceedings of the International Conference on Embedded Systems and Applications, 2003
A Low Power Algorithm for Reconfigurable VLSI/WSI Arrays.
Proceedings of the International Conference on Embedded Systems and Applications, 2003
2002
Heuristic techniques for accelerating hierarchical routing on road networks.
IEEE Trans. Intell. Transp. Syst., 2002
A novel technique for eliminating iterative based computation of polarity of micro-rotations in CORDIC based sine-cosine generators.
Microprocess. Microsystems, 2002
Area-time issues in the VLSI implementation of self organizing map neural networks.
Microprocess. Microsystems, 2002
A linear approximation based hybrid approach for binary logarithmic conversion.
Microprocess. Microsystems, 2002
Segmenting endoscopic images using adaptive progressive thresholding: a hardware perspective.
J. Syst. Archit., 2002
Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method.
J. Intell. Robotic Syst., 2002
On Load Sharing in Distributed Systems: a Novel Approach.
Trans. SDPS, 2002
Field programable gate array based architecture for real time image segmentation by region growing algorithm.
J. Electronic Imaging, 2002
Optimizing Scaling Factor Computations in Flat Cordic.
J. Circuits Syst. Comput., 2002
Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction.
Proceedings of the 5th IEEE Southwest Symposium on Image Analysis and Interpretation, 2002
Load Sharing in Large Scale Distributed Systems: A Novel Approach.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
A Hardware Efficient Technique for Rapid Lumen Segmentation from Endoscopic Images.
Proceedings of the 6th Joint Conference on Information Science, 2002
Multiple sequence families with efficient hardware architecture for use in spread spectrum watermarking.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
New Architecture and Algorithms for Degradable VLSI/WSI Arrays.
Proceedings of the Computing and Combinatorics, 8th Annual International Conference, 2002
An efficient architecture for adaptive progressive thresholding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Fuzzy-ART based image compression for hardware implementation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Incorporating area-time flexibility to a binary signed-digit adder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
A MSB-biased self-organizing feature map for still color image compression.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Network Simulation Environment (NSE): A Generic Framework for Network Graphs.
Telecommun. Syst., 2001
High-Speed Environment Representation Scheme for Dynamic Path Planning.
J. Intell. Robotic Syst., 2001
A Recursive Otsu-Iris Filter Technique for High-Speed Detection of Lumen Region from Endoscopic Images.
Proceedings of the 30th Applied Image Pattern Recognition Workshop (AIPR 2001), 2001
2000
Dynamic multicast routing in VLSI.
Comput. Commun., 2000
A Robust Parallel Architecture for Adaptive Color Quantization.
Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000
A High Speed Flat CORDIC Based Neuron with Multi-Level Activation Function for Robust Pattern Recognition.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000
1999
A pipelined architecture for image segmentation by adaptive progressive thresholding.
Microprocess. Microsystems, 1999
Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}.
Proceedings of the IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 1999
LSP parameter interpretation for speech classification.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
New area efficient residue-to-weighted number system converters.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999
A Reverse Converter for the 4-moduli Superset {2<sup>n-1</sup>, 2<sup>n</sup>, 2<sup>n+1</sup>, 2<sup>n+1</sup>+1}.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999
1998
An OLE-based speech compression system for multimedia applications.
Microprocess. Microsystems, 1998
An Internet application for on-line banking.
Comput. Commun., 1998
Designing efficient residue arithmetic based VLSI correlators.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
An Object Oriented GUI for Clustering Technique Based Network Simulations.
Proceedings of the 12<sup>th</sup> European Simulation Multiconference - Simulation, 1998
1997
An efficient adaptive routing algorithm for a network management system.
Comput. Commun., 1997
1996
An Efficient Adaptive Routing Strategy for Network Management Protocol.
Proceedings of the Modelling and Simulation, 1996
1995
A transputer based vehicle simulator.
Microprocess. Microsystems, 1995