A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Supporting ordinal four-state classification decisions using neural networks.
Inf. Technol. Manag., 2001