MLPerf™ HPC: A Holistic Benchmark Suite for Scientific Machine Learning on HPC Systems.
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Proceedings of the IEEE/ACM Workshop on Machine Learning in High Performance Computing Environments, 2021
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
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Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.
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Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC.
IEEE J. Solid State Circuits, 2015
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS.
IEEE J. Solid State Circuits, 2014
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique.
Proceedings of the Symposium on VLSI Circuits, 2014
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.
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IEEE J. Solid State Circuits, 2013
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.
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Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012