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2006
A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.
[DOI]
Churoo Park
,
Hoeju Chung
,
Yun-Sang Lee
,
Jaekwan Kim
,
JaeJun Lee
,
Moo Sung Chae
,
Dae-Hee Jung
,
Sung-Ho Choi
,
Seung-young Seo
,
Taek-Seon Park
,
Jun-Ho Shin
,
Jin-Hyung Cho
,
Seunghoon Lee
,
Ki-Whan Song
,
Kyu-Hyoun Kim
,
Jung-Bae Lee
,
Changhyun Kim
,
Soo-In Cho
IEEE J. Solid State Circuits, 2006