A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2024
Multi-Level Prototyping of a Vertical Vector AI Processing System.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024
PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
N<sup>2</sup>V<sup>2</sup>PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture.
Proceedings of the 13th IEEE International Conference on Consumer Electronics - Berlin, 2023
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving.
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Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments.
Int. J. Parallel Program., 2021
Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019