A DSP architecture optimized for wireless baseband.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Retrospective: the J-machine.
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Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998
Thread scheduling mechanisms for multiple-context parallel processors.
PhD thesis, 1995
Thread prioritization: A thread scheduling mechanism for multiple-context parallel processors.
Future Gener. Comput. Syst., 1995
The message-driven processor: a multicomputer processing node with efficient mechanisms.
IEEE Micro, 1992
The Message Driven Processor: An Integrated Multicomputer Processing Element.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
The J-Machine: A Fine-Gain Concurrent Computer.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
The Reconfigurable Arithmetic Processor.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988