Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications.

Color video encryption transmission in IoT based on memristive hopfield neural network.

Multiscroll hopfield neural network with extreme multistability and its application in video encryption for IIoT.

A general task offloading and resources allocation strategy for multi-RSUs with load unbalance and priority awareness.

DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks.

A quantum convolution and neighborhood pixel extraction scheme based on NEQR.

Analysis and Design of a Low-Voltage Low-Power High SNDR Current-Mode Sample and Hold Circuit Based on CMOS Technology.

Dynamic Analysis, Image Encryption Application and FPGA Implementation of a Discrete Memristor-Coupled Neural Network.

Memristor-induced hyperchaos, multiscroll and extreme multistability in fractional-order HNN: Image encryption and FPGA implementation.

Dynamic analysis and FPGA implementation of a 5D multi-wing fractional-order memristive chaotic system with hidden attractors.

A self-attention-LSTM method for dam deformation prediction based on CEEMDAN optimization.

A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation.

Vehicle Stability Analysis by Zero Dynamics to Improve Control Performance.

A secure scan architecture using parallel latch-based lock.

Dynamics analysis, FPGA realization and image encryption application of a 5D memristive exponential hyperchaotic system.

Four-input-C-element-based multiple-node-upset-self-recoverable latch designs.

A highly reliable and low-power cross-coupled 18T SRAM cell.

Privacy Protection of Medical Data Based on Multi-Scroll Memristive Hopfield Neural Network.

Complex Dynamics, Hardware Implementation and Image Encryption Application of Multiscroll Memeristive Hopfield Neural Network With a Novel Local Active Memeristor.

Low-power and high-speed SRAM cells for double-node-upset recovery.

Three-Dimensional Marine Ranching Cage Inspection Path Planning Integrating the Differential Evolution and Particle Swarm Optimization Algorithms.

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture.

A novel intelligent hyper-heuristic algorithm for solving optimization problems.

Feature extraction method of multi-frame image in cloud video.

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation.

Open-source dataset of vehicle state for an electric vehicle on a low-adhesion road.

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.

A new multi-scroll Chua's circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application.

Chaos-Based Engineering Applications with a 6D Memristive Multistable Hyperchaotic System and a 2D SF-SIMM Hyperchaotic Map.

A 1 V, 0.53 ns, 59 μW Current Comparator Using Standard 0.18 μm CMOS Technology.

A New 4D Four-Wing Memristive Hyperchaotic System: Dynamical Analysis, Electronic Circuit Design, Shape Synchronization and Secure Communication.

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.

Secure Communication Scheme Based on a New 5D Multistable Four-Wing Memristive Hyperchaotic System with Disturbance Inputs.

CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua's Chaotic System with Coexisting Multiple Attractors.

Dynamic Analysis, Circuit Design, and Synchronization of a Novel 6D Memristive Four-Wing Hyperchaotic System with Multiple Coexisting Attractors.

Chaos-Based Application of a Novel Multistable 5D Memristive Hyperchaotic System with Coexisting Multiple Attractors.

Pseudorandom Number Generator Based on Three Kinds of Four-Wing Memristive Hyperchaotic System and Its Application in Image Encryption.

An Efficient Degraded Deductive Fault Simulator for Small-Delay Defects.

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications.

A robust and fixed-time zeroing neural dynamics for computing time-variant nonlinear equation using a novel nonlinear activation function.

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits.

Analysis and FPGA Realization of a Novel 5D Hyperchaotic Four-Wing Memristive System, Active Control Synchronization, and Secure Communication Application.

Design and FPGA Implementation of a Pseudorandom Number Generator Based on a Four-Wing Memristive Hyperchaotic System and Bernoulli Map.

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks.

A novel test data compression approach based on bit reversion.

Reliability evaluation of logic circuits based on transient faults propagation metrics.

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.

An efficient small-delay faults simulator based on critical path tracing.

Harzard-Based ATPG for Improving Delay Test Quality.

Low power logic BIST with high test effectiveness.