A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.
Proceedings of the 25th International Conference on VLSI Design, 2012
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.
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Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An IA-32 processor with a wide voltage operating range in 32nm CMOS.
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Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
IEEE J. Solid State Circuits, 2011
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
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IEEE J. Solid State Circuits, 2011
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2010