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2020
A High Throughput and Pipelined Implementation of the LUKS on FPGA.
[DOI]
Xiaochao Li
,
Kongcheng Wu
,
Qi Zhang
,
Shaoyu Lin
,
Yihui Chen
,
Shen Yuong Wong
J. Circuits Syst. Comput., 2020
2019
High-throughput and area-efficient fully-pipelined hashing cores using BRAM in FPGA.
[DOI]
Lin Li
,
Shaoyu Lin
,
Shuli Shen
,
Kongcheng Wu
,
Xiaochao Li
,
Yihui Chen
Microprocess. Microsystems, 2019