Computational Storage For Big Data Analytics.
Proceedings of the 10th International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2019
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
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Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
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Proceedings of the 53rd Annual Design Automation Conference, 2016
In-depth soft error vulnerability analysis using synthetic benchmarks.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Efficient soft error vulnerability estimation of complex designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Fast evaluation of test vector sets using a simulation-based statistical metric.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
EAGLE: A regression model for fault coverage estimation using a simulation based metric.
Proceedings of the 2014 International Test Conference, 2014
Rethinking error injection for effective resilience.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Quantitative evaluation of soft error injection techniques for robust system design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
FALCON: Rapid statistical fault coverage estimation for complex designs.
Proceedings of the 2012 IEEE International Test Conference, 2012
RT level reliability enhancement by constructing dynamic TMRS.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.
Proceedings of the Forum on specification and Design Languages, 2007
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs.
Proceedings of the 15th Asian Test Symposium, 2006
Enhancing Fault Simulation Performance by Dynamic Fault Clustering.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electron. Test., 2004
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Fault Simulation for VHDL Based Test Bench and BIST Evaluation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001