2015
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 4-GHz universal high-frequency on-chip testing platform for IP validation.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm<sup>2</sup> per MB.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Prospective for nanowire transistors.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2008
Challenges at 45nm and beyond.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2007
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
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IBM J. Res. Dev., 2007
Cell Broadband Engine Processor Design Methodology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Implementation of the 65nm Cell Broadband Engine.
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Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor.
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IEEE J. Solid State Circuits, 2006
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.
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IEEE J. Solid State Circuits, 2006
The microarchitecture of the synergistic processor for a cell processor.
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IEEE J. Solid State Circuits, 2006
A cycle accurate power estimation tool.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Power-Conscious Design of the Cell Processor's Synergistic Processor Element.
IEEE Micro, 2005
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.
IEEE Micro, 2005
The circuit design of the synergistic processor element of a CELL processor.
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Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.
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Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2000
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
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IEEE J. Solid State Circuits, 2000
Custom circuit design as a driver of microprocessor performance.
IBM J. Res. Dev., 2000
"Timing closure by design, " a high frequency microprocessor design methodology.
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Proceedings of the 37th Conference on Design Automation, 2000
1999
A 1-GHz logic circuit family with sense amplifiers.
IEEE J. Solid State Circuits, 1999
1998
Designing for a gigahertz [guTS integer processor].
IEEE Micro, 1998
A 1.0-GHz single-issue 64-bit powerPC integer processor.
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IEEE J. Solid State Circuits, 1998
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
A 690 ps read-access latency register file for a GHz integer microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Design methodology for a 1.0 GHz microprocessor.
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Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1995
A variable precharge voltage sensing.
IEEE J. Solid State Circuits, January, 1995
A 64Kb - 32 DRAM for graphics applications.
IBM J. Res. Dev., 1995
A low-noise TTL-compatible CMOS off-chip driver circuit.
IBM J. Res. Dev., 1995
1992
A 14-ns 14-Mb CMOS DRAM with 300-mW active power.
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IEEE J. Solid State Circuits, September, 1992
A large V<sub>DS</sub> data retention test pattern for DRAM's.
IEEE J. Solid State Circuits, August, 1992
A pulsed sensing scheme with a limited bit-line swing.
IEEE J. Solid State Circuits, April, 1992
1989
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.
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IEEE J. Solid State Circuits, October, 1989
1988
High-speed sensing scheme for CMOS DRAMs.
IEEE J. Solid State Circuits, February, 1988