Topic 4: High-Performance Architectures and Compilers - (Introduction).
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
On the convergence of mainstream and mission-critical markets.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments.
ACM Trans. Archit. Code Optim., 2012
The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform.
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Int. J. Parallel Program., 2011
Towards improved survivability in safety-critical systems.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
CMA: Chip multi-accelerator.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010
A memory interface for multi-purpose multi-stream accelerators.
Proceedings of the 2010 International Conference on Compilers, 2010
Reconciling specialization and flexibility through compound circuits.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007
Load squared: Adding logic close to memory to reduce the latency of indirect loads in embedded and general systems.
J. Embed. Comput., 2006
Scalable subgraph mapping for acyclic computation accelerators.
Proceedings of the 2006 International Conference on Compilers, 2006
Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.
SIGARCH Comput. Archit. News, 2005
System-wide performance monitors and their application to the optimization of coherent memory accesses.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005
Exploring the design space of LUT-based transparent accelerators.
Proceedings of the 2005 International Conference on Compilers, 2005
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004