15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10<sup>12</sup> Write Endurance and Integrated Margin-Expansion Schemes.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm<sup>2</sup> and 3.78Mb/mm<sup>2</sup> Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
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IEEE J. Solid State Circuits, 2014
A novel DFT architecture for 3DIC test, diagnosis and repair.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS<sup>TM</sup>/3D ICs.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
The importance of DFX, a foundry perspective.
Proceedings of the 2014 International Test Conference, 2014
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.
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Proceedings of the 2013 IEEE International Test Conference, 2013
Improved Core Isolation and Access for Hierarchical Embedded Test.
IEEE Des. Test Comput., 2009
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004
Comprehensive defect analysis and testability of current-mode logic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Comparing defect coverage for current-mode logic and CMOS VLSI cells.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Scan-based BIST fault diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Linking diagnostic software to hardware self test in telecom systems.
IEEE Commun. Mag., 1999
Design For Testability Method for CML Digital Circuits.
Proceedings of the 1999 Design, 1999
Test Reuse at System Level.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
BIST Fault Diagnosis in Scan-Based VLSI Environments.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
A New Hardware Fault Insertion Scheme for System Diagnostics Verification.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Linking Diagnostic Software to Hardware Self Test in Telecom Systems.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995