2024
Improving Speech Translation Accuracy and Time Efficiency With Fine-Tuned wav2vec 2.0-Based Speech Segmentation.
IEEE ACM Trans. Audio Speech Lang. Process., 2024

NAIST Simultaneous Speech Translation System for IWSLT 2024.
CoRR, 2024

NTTSU at WMT2024 General Translation Task.
Proceedings of the Ninth Conference on Machine Translation, 2024

NAIST-SIC-Aligned: An Aligned English-Japanese Simultaneous Interpretation Corpus.
Proceedings of the 2024 Joint International Conference on Computational Linguistics, 2024

2023
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface.
IEEE J. Solid State Circuits, 2023

NAIST-SIC-Aligned: Automatically-Aligned English-Japanese Simultaneous Interpretation Corpus.
CoRR, 2023

Tagged End-to-End Simultaneous Speech Translation Training Using Simultaneous Interpretation Data.
Proceedings of the 20th International Conference on Spoken Language Translation, 2023

NAIST Simultaneous Speech-to-speech Translation System for IWSLT 2023.
Proceedings of the 20th International Conference on Spoken Language Translation, 2023

2022
NAIST Simultaneous Speech-to-Text Translation System for IWSLT 2022.
Proceedings of the 19th International Conference on Spoken Language Translation, 2022

A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Speech Segmentation Optimization using Segmented Bilingual Speech Corpus for End-to-end Speech Translation.
Proceedings of the 23rd Annual Conference of the International Speech Communication Association, 2022

2021
A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs.
IEEE J. Solid State Circuits, 2021

Simultaneous Speech-to-Speech Translation System with Transformer-Based Incremental ASR, MT, and TTS.
Proceedings of the 24th Conference of the Oriental COCOSDA International Committee for the Co-ordination and Standardisation of Speech Databases and Assessment Techniques, 2021

On Knowledge Distillation for Translating Erroneous Speech Transcriptions.
Proceedings of the 18th International Conference on Spoken Language Translation, 2021

NAIST English-to-Japanese Simultaneous Translation System for IWSLT 2021 Simultaneous Text-to-text Task.
Proceedings of the 18th International Conference on Spoken Language Translation, 2021

30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology.
IEEE J. Solid State Circuits, 2020

NAIST's Machine Translation Systems for IWSLT 2020 Conversational Speech Translation Task.
Proceedings of the 17th International Conference on Spoken Language Translation, 2020

2019
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2011
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits, 2011

2010
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits, 2010

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Log-aesthetic space curve segments.
Proceedings of the 2009 ACM Symposium on Solid and Physical Modeling, 2009

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Logarithmic Curvature and Torsion Graphs.
Proceedings of the Mathematical Methods for Curves and Surfaces, 2008

2000
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.
IEEE J. Solid State Circuits, 2000