2025
Alchemy : A Methodology for Scalable RTL Design Space Exploration.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

2024
Seer: Predictive Runtime Kernel Selection for Irregular Problems.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023
Evaluation of a Modular Approach to AES Hardware Architecture and Optimization.
J. Signal Process. Syst., July, 2023

Parallelization of the Shift and Add Reducer.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2021
A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
An Improved Hardware Architecture for modulo without Multiplication.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020