An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS.

[DOI]

Jihang Gao

Siyuan Ye

Jie Li

IEEE J. Solid State Circuits, February, 2025

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array.

[DOI]

IEEE J. Solid State Circuits, January, 2025

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals.

[DOI]

CoRR, January, 2025

Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells.

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6x10-9 Bit Error Rate Through Efficient Redundancy Strategy.

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

An RRAM-Based Hierarchical Computing-in-Memory Architecture With Synchronous Parallelism for 3-D Point Cloud Recognition.

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, October, 2024

DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

DRGA-Based Second-Order Block Arnoldi Method for Model Order Reduction of MIMO RCS Circuits.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.

[DOI]

IEEE J. Solid State Circuits, March, 2024

Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.

[DOI]

IEEE J. Solid State Circuits, February, 2024

A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC.

[DOI]

IEEE J. Solid State Circuits, February, 2024

MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC.

[DOI]

CoRR, 2024

MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers.

[DOI]

CoRR, 2024

AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference.

[DOI]

CoRR, 2024

The Exploration-Exploitation Dilemma Revisited: An Entropy Perspective.

[DOI]

CoRR, 2024

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design.

[DOI]

CoRR, 2024

FastQuery: Communication-efficient Embedding Table Query for Private LLM Inference.

[DOI]

CoRR, 2024

PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction.

[DOI]

CoRR, 2024

ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel Decoding.

[DOI]

CoRR, 2024

Efficient yet Accurate End-to-End SC Accelerator Design.

[DOI]

CoRR, 2024

AttentionLego: An Open-Source Building Block For Spatially-Scalable Large Language Model Accelerator With Processing-In-Memory Technology.

[DOI]

CoRR, 2024

Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network.

[DOI]

Sci. China Inf. Sci., 2024

Hole mobility enhancement in monolayer WSe2 p-type transistors through molecular doping.

[DOI]

Sci. China Inf. Sci., 2024

An isolated symmetrical 2T2R cell enabling high precision and high density for RRAM-based in-memory computing.

[DOI]

Sci. China Inf. Sci., 2024

Post-layout simulation driven analog circuit sizing.

[DOI]

Sci. China Inf. Sci., 2024

First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects.

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup.

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis.

[DOI]

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Investigation of Positive Bias Temperature Instability in advanced FinFET nodes.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Convolution-Based Vth Shift Prediction and the New 9T2C Pixel Circuit in LTPS TFT AMOLED.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Sub-20-nm DRAM Technology under Negative Bias Temperature Instability (NBTI): from Characterization to Physical Origin Identification.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

New Insights into the Random Telegraph Noise (RTN) in FinFETs at Cryogenic Temperature.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Investigation of Interplays between Body Biasing and Hot Carrier Degradation (HCD) in Advanced NMOS FinFETs.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Accelerating Device-Circuit Self-Heating Simulations with Dynamic Time Evolution for GAAFET.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment.

[DOI]

Proceedings of the Twelfth International Conference on Learning Representations, 2024

SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge Security.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Heterogeneous Static Timing Analysis with Advanced Delay Calculator.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration.

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator.

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference.

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration.

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning.

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology.

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input.

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

Statistical Compact Modeling With Artificial Neural Networks.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Research progress on low-power artificial intelligence of things (AIoT) chip design.

[DOI]

Sci. China Inf. Sci., October, 2023

Memristive dynamics enabled neuromorphic computing systems.

[DOI]

Bonan Yan

Yuchao Yang

Ru Huang

Sci. China Inf. Sci., October, 2023

Neuromorphic Artificial Vision Systems Based on Reconfigurable Ion-Modulated Memtransistors.

[DOI]

Adv. Intell. Syst., August, 2023

Extremely-Fast, Energy-Efficient Massive MIMO Precoding With Analog RRAM Matrix Computing.

[DOI]

Pushen Zuo

Zhong Sun

Ru Huang

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

Experimental investigation of a novel junction-modulated hetero-layer tunnel FET with the striped gate for low power applications.

[DOI]

Sci. China Inf. Sci., June, 2023

A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Interactive Analog Layout Editing With Instant Placement and Routing Legalization.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Hadamard product-based in-memory computing design for floating point neural network training.

[DOI]

Neuromorph. Comput. Eng., March, 2023

Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis.

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference.

[DOI]

CoRR, 2023

HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction.

[DOI]

CoRR, 2023

EBSR: Enhanced Binary Neural Network for Image Super-Resolution.

[DOI]

CoRR, 2023

Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence.

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference.

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation.

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control.

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Investigation of Hot Carrier Enhanced Body Bias Effect in Advanced FinFET Technology.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing.

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A High-Throughput and Configurable TRNG Based on Dual-Mode Memristor for Stochastic Computing.

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

MPCViT: Searching for Accurate and Efficient MPC-Friendly Vision Transformer with Heterogeneous Attention.

[DOI]

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization.

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference.

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.

[DOI]

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

New Insights into Read Current Margin and Memory Window of HfO2-based Ferroelectric FET with Re-exploration of the Role of Ferroelectric Dynamics and Interface Charges during Readout.

[DOI]

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion.

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line.

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network.

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation.

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications.

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Not your father's stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design.

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Device-Architecture Co-optimization for RRAM-based In-memory Computing.

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System.

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Memristive devices based hardware for unlabeled data processing.

[DOI]

Neuromorph. Comput. Eng., 2022

MPCViT: Searching for MPC-friendly Vision Transformer with Heterogeneous Attention.

[DOI]

CoRR, 2022

Physical investigation of subthreshold swing degradation behavior in negative capacitance FET.

[DOI]

Sci. China Inf. Sci., 2022

Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors.

[DOI]

Sci. China Inf. Sci., 2022

Single event transients induced by pulse laser in Ge pMOSFETs and its supply voltage dependence.

[DOI]

Sci. China Inf. Sci., 2022

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA).

[DOI]

Sci. China Inf. Sci., 2022

In Materia Neuron Spiking Plasticity for Sequential Event Processing Based on Dual-Mode Memristor.

[DOI]

Adv. Intell. Syst., 2022

Artificial Multisensory Neurons with Fused Haptic and Temperature Perception for Multimodal In-Sensor Computing.

[DOI]

Adv. Intell. Syst., 2022

A Novel Ambipolar Ferroelectric Tunnel FinFET based Content Addressable Memory with Ultra-low Hardware Cost and High Energy Efficiency for Machine Learning.

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography.

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network.

[DOI]

Meng-Fan Marvin Chang

Tianchan Guan

Xin Si

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Compact Modeling of Phase Change Memory with Parameter Extractions.

[DOI]

Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis.

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme.

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications.

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

A Mapping Model of SNNs to Neuromorphic Hardware.

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Time Complexity of In-Memory Matrix-Vector Multiplication.

[DOI]

Zhong Sun

Ru Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Optimization Schemes for In-Memory Linear Regression Circuit With Memristor Arrays.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.

[DOI]

IEEE J. Solid State Circuits, 2021

A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network.

[DOI]

IEEE J. Solid State Circuits, 2021

Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.

[DOI]

IEEE J. Solid State Circuits, 2021

Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET.

[DOI]

Sci. China Inf. Sci., 2021

In-memory computing with emerging nonvolatile memory devices.

[DOI]

Sci. China Inf. Sci., 2021

12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 16 Overview: Computation in Memory Memory Subcommittee.

[DOI]

Meng-Fan Chang

Ru Huang

Seung-Jun Bae

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

DALTA: A Decomposition-based Approximate Lookup Table Architecture.

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA.

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing.

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Circuit Reliability Comparison Between Stochastic Computing and Binary Computing.

[DOI]

IEEE Trans. Circuits Syst., 2020

Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators.

[DOI]

IEEE Trans. Circuits Syst., 2020

DaSGD: Squeezing SGD Parallelization Performance in Distributed Training Using Delayed Averaging.

[DOI]

CoRR, 2020

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors.

[DOI]

Sci. China Inf. Sci., 2020

High-quality and large-grain epi-like Si film by NiSi2-seed initiated lateral epitaxial crystallization (SILEC).

[DOI]

Sci. China Inf. Sci., 2020

Vertical SnS2/Si heterostructure for tunnel diodes.

[DOI]

Rundong Jia

Qianqian Huang

Ru Huang

Sci. China Inf. Sci., 2020

Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure.

[DOI]

Sci. China Inf. Sci., 2020

A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor.

[DOI]

Sci. China Inf. Sci., 2020

Memristor-Based Biologically Plausible Memory Based on Discrete and Continuous Attractor Networks for Neuromorphic Systems.

[DOI]

Adv. Intell. Syst., 2020

Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor.

[DOI]

Adv. Intell. Syst., 2020

20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis.

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing.

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework.

[DOI]

CoRR, 2019

A Parallel Bitstream Generator for Stochastic Computing.

[DOI]

CoRR, 2019

Deep insight into the voltage amplification effect from ferroelectric negative capacitance.

[DOI]

Sci. China Inf. Sci., 2019

Low power and high uniformity of HfO x -based RRAM via tip-enhanced electric fields.

[DOI]

Sci. China Inf. Sci., 2019

Investigation of NbOx-based volatile switching device with self-rectifying characteristics.

[DOI]

Sci. China Inf. Sci., 2019

Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing.

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Survey of Computation-Driven Data Encoding.

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model.

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training.

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits.

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Realization of Nanoscale Neuromorphic Memristor Array with Low Power Consumption.

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Neuromorphic Devices and Networks Based on Memristors with Ionic Dynamics.

[DOI]

Yuchao Yang

Ke Yang

Ru Huang

Proceedings of the Handbook of Memristor Networks., 2019

2018

Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits.

[DOI]

Microelectron. Reliab., 2018

Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology.

[DOI]

Sci. China Inf. Sci., 2018

GeC film with high substitutional carbon concentration formed by ion implantation and solid phase epitaxy for strained Ge n-MOSFETs.

[DOI]

Sci. China Inf. Sci., 2018

Integration of biocompatible organic resistive memory and photoresistor for wearable image sensing application.

[DOI]

Sci. China Inf. Sci., 2018

Margin Dependence on Array Size for Asymmetric Resistive Memory Cell.

[DOI]

Proceedings of the Non-Volatile Memory Technology Symposium, 2018

Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer.

[DOI]

Proceedings of the Non-Volatile Memory Technology Symposium, 2018

A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Compact modeling and simulation of accelerated circuit aging.

[DOI]

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition.

[DOI]

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

Layout-dependent aging mitigation for critical path timing.

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Compact digital-controlled neuromorphic circuit with low power consumption.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Benchmarking TFET from a circuit level perspective: Applications and guideline.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator.

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing.

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device.

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Switching dynamics and computing applications of memristors: An overview.

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Editor's note.

[DOI]

Sci. China Inf. Sci., 2016

Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life.

[DOI]

Pengpeng Ren

Runsheng Wang

Ru Huang

Proceedings of the International Conference on IC Design and Technology, 2016

A 3D multi-layer CMOS-RRAM accelerator for neural network.

[DOI]

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS.

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling.

[DOI]

Sci. China Inf. Sci., 2015

Ge surface passivation by GeO2 fabricated by N2O plasma oxidation.

[DOI]

Sci. China Inf. Sci., 2015

An electronic synapse based on tantalum oxide material.

[DOI]

Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Influence of selector-introduced compliance current on HfOx RRAM switching operation.

[DOI]

Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology.

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.

[DOI]

CoRR, 2014

A novel low-noise high-linearity CMOS transmitter for mobile UHF RFID reader.

[DOI]

Sci. China Inf. Sci., 2014

Resistive switching in organic memory devices for flexible applications.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A comb-gate silicon tunneling field effect transistor with improved on-state current.

[DOI]

Sci. China Inf. Sci., 2013

Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors.

[DOI]

Sci. China Inf. Sci., 2013

A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process.

[DOI]

Sci. China Inf. Sci., 2013

Heterogeneous integration of nano enabling devices for 3D ICs.

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter.

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A novel compact low-power direct conversion receiver for mobile UHF RFID reader.

[DOI]

Sci. China Inf. Sci., 2012

Theory and verification of operator design methodology.

[DOI]

Sci. China Inf. Sci., 2012

Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis.

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Widely reconfigurable 8th-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS.

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads.

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique.

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors.

[DOI]

Microelectron. Reliab., 2011

Editor's note.

[DOI]

Sci. China Inf. Sci., 2011

Resistance switching for RRAM applications.

[DOI]

Sci. China Inf. Sci., 2011

A 0.47mW 6th-order 20MHz active filter using highly power-efficient Opamp.

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An ultra-low power 400MHz OOK transceiver for medical implanted applications.

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling.

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Deteriorated radiation effects impact on the characteristics of MOS transistors with multi-finger configuration.

[DOI]

Microelectron. Reliab., 2010

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications.

[DOI]

IEEE J. Solid State Circuits, 2010

2009

Challenges of 22 nm and beyond CMOS technology.

[DOI]

Sci. China Ser. F Inf. Sci., 2009

A single-chip CMOS UHF RFID Reader transceiver for mobile applications.

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

Novel devices and process for 32 nm CMOS technology and beyond.

[DOI]

Sci. China Ser. F Inf. Sci., 2008

Novel vertical channel double gate structures for high density and low power flash memory applications.

[DOI]

Sci. China Ser. F Inf. Sci., 2008

2003

Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration.

[DOI]

Microelectron. Reliab., 2003

2002

Application of forward gated-diode R-G current method in extracting F-N stress-induced interface traps in SOI NMOSFETs.

[DOI]

Microelectron. Reliab., 2002

2001

Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique.

[DOI]

Microelectron. Reliab., 2001

Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile.

[DOI]

Sci. China Ser. F Inf. Sci., 2001