2010
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration.
IEEE J. Solid State Circuits, 2010

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2006
A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter.
IEEE J. Solid State Circuits, 2006

2005
A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005