2018
AnRAD: A Neuromorphic Anomaly Detection Framework for Massive Concurrent Data Streams.
IEEE Trans. Neural Networks Learn. Syst., 2018
2015
Self-structured confabulation network for fast anomaly detection and reasoning.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
2014
Memristor Crossbar-Based Neuromorphic Computing System: A Case Study.
IEEE Trans. Neural Networks Learn. Syst., 2014
2013
A Parallel Neuromorphic Text Recognition System and Its Implementation on a Heterogeneous High-Performance Computing Cluster.
IEEE Trans. Computers, 2013
2011
Unified perception-prediction model for context aware text recognition on a heterogeneous many-core platform.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Parallel flux tensor analysis for efficient moving object detection.
Proceedings of the 14th International Conference on Information Fusion, 2011
Confabulation based sentence completion for machine reading.
Proceedings of the 2011 IEEE Symposium on Computational Intelligence, 2011
2010
Neuromorphic algorithms on clusters of PlayStation 3s.
Proceedings of the International Joint Conference on Neural Networks, 2010
A columnar primary visual cortex (V1) model emulation using a PS3 Cell-BE array.
Proceedings of the International Joint Conference on Neural Networks, 2010
Affordable emerging computer hardware for neuromorphic computing applications.
Proceedings of the International Joint Conference on Neural Networks, 2010
Emerging neuromorphic computing architectures & enabling hardware for cognitive information processing applications.
Proceedings of the 2nd International Workshop on Cognitive Information Processing, 2010
GPGPU role within a 500 TFLOPS heterogeneous cluster.
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010
2008
Using metrics to optimize a high performance intelligent image processing code.
Proceedings of the 8th Workshop on Performance Metrics for Intelligent Systems, 2008
Accelerating cogent confabulation: An exploration in the architecture design space.
Proceedings of the International Joint Conference on Neural Networks, 2008
Performance optimization for pattern recognition using associative neural memory.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
Fault tolerant integrated information management support for physically constrained iterative deconvolution.
Proceedings of the 37th IEEE Applied Imagery Pattern Recognition Workshop, 2008
2007
Information management for high performance autonomous intelligent systems.
Proceedings of the 2007 Workshop on Performance Metrics for Intelligent Systems, 2007
Architectural Design and Complexity Analysis of Large-Scale Cortical Simulation on a Hybrid Computing Platform.
Proceedings of the 2007 IEEE Symposium on Computational Intelligence in Security and Defense Applications, 2007
Imagery Pattern Recognition and Pub/Sub Information Management.
Proceedings of the 36th Applied Imagery Pattern Recognition Workshop, 2007
2006
Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006
Limiting Optimism: Time or Event Count?
Proceedings of the 10th IEEE International Symposium on Distributed Simulation and Real-Time Applications (DS-RT 2006), 2006
Application Development Framework for the Rapid Integration of High Performance Image Processing Algorithms.
Proceedings of the 35th Applied Image Pattern Recognition Workshop (AIPR 2006), 2006
2005
Using globus grid objects to extend a corba-based object-oriented system.
Proceedings of the Companion to the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2005
2003
Redeveloping a high-Performance computing framework.
Proceedings of the Companion of the 18th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2003
2002
A FrameWork for high-performance image exploitation.
Proceedings of the Companion of the 17th annual ACM SIGPLAN conference on Object-oriented programming, 2002
2000
Design, implementation and evaluation of parallel pipelined STAP on parallel computers.
IEEE Trans. Aerosp. Electron. Syst., 2000
1998
A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing.
IEEE Trans. Computers, 1998
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
1989
Design and application of an optimizing XROM silicon compiler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
1988
A 70-MHz 1.2- mu m CMOS 16-point DFT processor.
IEEE J. Solid State Circuits, April, 1988
1984
Digital signal processing capabilities of CUSP, a high performance bit-serial VLSI processor.
Proceedings of the IEEE International Conference on Acoustics, 1984
A three dimensional systolic array architecture for fast matrix multiplication.
Proceedings of the IEEE International Conference on Acoustics, 1984