Eh-DRVP: Combining placement and global routing data in a hyper-image-based DRV predictor.
Integr., 2025
GRCMO: Global Routing Optimization by Median-Based Cell Movement.
Proceedings of the 16th IEEE Latin America Symposium on Circuits and Systems, 2025
ILPGRC: ILP-Based Global Routing Optimization With Cell Movements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes.
ACM Trans. Design Autom. Electr. Syst., September, 2023
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
E-RVP: An Initial Design Rule Violation Predictor Using Placement Information.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
CR&P: An Efficient Co-operation between Routing and Placement.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
ILP-Based Global Routing Optimization with Cell Movements.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization.
Proceedings of the 2019 International Symposium on Physical Design, 2019
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Exploiting cache locality to speedup register clustering.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Clock-Tree-Aware Incremental Timing-Driven Placement.
ACM Trans. Design Autom. Electr. Syst., 2016
Evaluating the impact of circuit legalization on incremental optimization techniques.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Exploiting parallelism to speed up circuit legalization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
VLSI architectures for Digital Modulation Classification using Support Vector Machines.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013