2024
FitBit: Ensuring Robust and Secure Execution Through Runtime-Generated Stressmarks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
2023
Adaptive Power Shifting for Power-Constrained Heterogeneous Systems.
IEEE Trans. Computers, March, 2023
Characterization and Exploration of Latch Checkers for Efficient RAS Protection.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
2022
AI accelerator on IBM telum processor: industrial product.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
2021
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption.
IEEE Trans. Computers, 2021
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15.
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IEEE J. Solid State Circuits, 2021
A matrix math facility for Power ISA(TM) processors.
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CoRR, 2021
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Energy Efficiency Boost in the AI-Infused POWER10 Processor.
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Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
SERMiner : A Framework for Early-stage Reliability Estimation for IBM Processors.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
2020
Proactive power management in IBM z15.
IBM J. Res. Dev., 2020
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor.
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Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
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IEEE J. Solid State Circuits, 2019
Asymmetric Resilience for Accelerator-Rich Systems.
IEEE Comput. Archit. Lett., 2019
Generation of Stressmarks for Early Stage Soft-Error Modeling.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
2018
IBM POWER9 circuit design and energy optimization for 14-nm technology.
IBM J. Res. Dev., 2018
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
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Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018
2017
Machine learning techniques for taming the complexity of modern hardware design.
IBM J. Res. Dev., 2017
26.2 Power supply noise in a 22nm z13™ microprocessor.
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Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
libPRISM: an intelligent adaptation of prefetch and SMT levels.
Proceedings of the International Conference on Supercomputing, 2017
Very Low Voltage (VLV) Design.
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Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
BRAVO: Balanced Reliability-Aware Voltage Optimization.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2015
Robust power management in the IBM z13.
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IBM J. Res. Dev., 2015
Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
2014
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Characterization of transient error tolerance for a class of mobile embedded applications.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
2013
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs.
IEEE Trans. Computers, 2013
Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems.
IBM J. Res. Dev., 2013
Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up.
Comput. J., 2013
2012
Energy accounting for shared virtualized environments under DVFS using PMC-based power models.
Future Gener. Comput. Syst., 2012
POTRA: a framework for building power models for next generation multicore architectures.
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
2011
Local Memory Design Space Exploration for High-Performance Computing.
Comput. J., 2011
Design space exploration for aggressive core replication schemes in CMPs.
Proceedings of the 20th ACM International Symposium on High Performance Distributed Computing, 2011
2010
Decomposable and responsive power models for multicore processors using performance counters.
Proceedings of the 24th International Conference on Supercomputing, 2010
Accurate energy accounting for shared virtualized environments using PMC-based power modeling techniques.
Proceedings of the 2010 11th IEEE/ACM International Conference on Grid Computing, 2010