An efficient protocol with synchronization accelerator for multi-processor embedded systems.
Parallel Comput., 2013
An efficient scheduler of RTOS for multi/many-core system.
Comput. Electr. Eng., 2012
A networks-on-chip emulation/verification framework.
Int. J. High Perform. Syst. Archit., 2011
Network interface design based on mutual interface definition.
Int. J. High Perform. Syst. Archit., 2010
A synergetic operating unit on NoC layer for CMP system.
Int. J. High Perform. Syst. Archit., 2010
A networks-on-chip architecture design space exploration - The LIB.
Comput. Electr. Eng., 2009
A NoC Emulation/Verification Framework.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009
A processor for MPEG decoder SOC: a software/hardware co-design approach.
Proceedings of the Electronic Imaging: Image and Video Communications and Processing 2005, 2005
Embedded software optimization for MP3 decoder implemented on RISC core.
IEEE Trans. Consumer Electron., 2004
Fast algorithm of arbitrary fractional-pixel accuracy motion estimation.
Proceedings of the Visual Communications and Image Processing 2002, 2002
Highly efficient simulation environment for HDTV video decoder in VLSI design.
Proceedings of the Visual Communications and Image Processing 2002, 2002
Hardware/software codesign for HDTV source decoder on system level.
Proceedings of the Visual Communications and Image Processing 2002, 2002
A bus arbitration scheme for HDTV decoder SoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Model-based coding for multiobject sequence.
Proceedings of the Visual Communications and Image Processing 2001, 2001
SPMD architecture for DSP-based data encryption communication system.
Proceedings of the Security and Watermarking of Multimedia Contents III, 2001
Novel video signal processor with VLIW-controlled SIMD architecture.
Proceedings of the Visual Communications and Image Processing 2000, 2000
A software/hardware co-design methodology for embedded microprocessor core design.
IEEE Trans. Consumer Electron., 1999
An Estimation of Low Bound for Two-Dimensional Image Compression Coding.
Proceedings of the Image Analysis Applications and Computer Graphics, 1995