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A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology.
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IEEE J. Solid State Circuits, 2017
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology.
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Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither.
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Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Web service based Grid workflow application in quantitative remote sensing retrieval.
Proceedings of the 2014 IEEE Geoscience and Remote Sensing Symposium, 2014
An agent-based adaptive join algorithm for building data warehouses.
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A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition.
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IEEE J. Solid State Circuits, 2006
Efficient approximation of symbolic network functions using matroid intersection algorithms.
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Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms.
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Approximate symbolic analysis of large analog integrated circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
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