Efficient execution of speculative threads and transactions with hardware transactional memory.
Future Gener. Comput. Syst., 2014
Priority-based squash reducing methods in thread level speculation.
Int. J. Inf. Technol. Commun. Convergence, 2012
A Speculative HMMER Search Implementation on GPU.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
SeTM: Efficient Execution of Speculative Threads with Hardware Transactional Memory.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Distributed Control Independence for Composable Multi-processors.
Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012
Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor.
Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012
A Non-blocking Programming Framework for Pipeline Application on Multi-core Platform.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011
A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011
FACRA: Flexible-Core Architecture Chip Resource Abstractor.
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010
Investigation of Factors Impacting Thread-Level Parallelism from Desktop, Multimedia and HPC Applications.
Proceedings of the Fourth International Conference on Frontier of Computer Science and Technology, 2009
LogSPoTM: a scalable thread level speculation model based on transactional memory.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008