A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
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Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Modeling and Power Evaluation of On-Chip Router Components in Spintronics.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012