Cross-layer resilience challenges: Metrics and optimization.
Proceedings of the Design, Automation and Test in Europe, 2010
Fault-Tolerant Design of the IBM Power6 Microprocessor.
IEEE Micro, 2008
Soft-error resilience of the IBM POWER6 processor.
IBM J. Res. Dev., 2008
Phaser: Phased methodology for modeling the system-level effects of soft errors.
IBM J. Res. Dev., 2008
Soft-error resilience of the IBM POWER6 processor input/output subsystem.
IBM J. Res. Dev., 2008
Statistical Fault Injection.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008
Soft Errors: System Effects, Protection Techniques and Case Studies.
Proceedings of the Design, Automation and Test in Europe, 2008
Soft Errors: Technology Trends, System Effects, and Protection Techniques.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Guest Editors' Introduction: Reliability-Aware Microarchitecture.
IEEE Micro, 2005
The concern for soft errors is not overblown.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Latchup Analysis Using Emission Microscopy.
Microelectron. Reliab., 2003
Optical and Electrical Testing of Latchup in I/O Interface Circuits.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability.
IEEE J. Solid State Circuits, 1999
The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA).
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Diagnosis and characterization of timing-related defects by time-dependent light emission.
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Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998