2025
Empowering healthcare with BIEH - blockchain inter-operable electronic health record scheme.
Clust. Comput., April, 2025
2018
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis.
Proceedings of the IEEE International Test Conference, 2018
An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug.
Proceedings of the IEEE International Test Conference, 2018
2015
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2013
NBTI-aware circuit node criticality computation.
ACM J. Emerg. Technol. Comput. Syst., 2013
2012
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.
ACM Trans. Embed. Comput. Syst., 2012
A physical design tool for carbon nanotube field-effect transistor circuits.
ACM J. Emerg. Technol. Comput. Syst., 2012
Test generation for clock-domain crossing faults in integrated circuits.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2011
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.
Proceedings of the Design, Automation and Test in Europe, 2011
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2008
Automatic Test Generation for Combinational Threshold Logic Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2008
2007
A Test Generation Framework for Quantum Cellular Automata Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
2006
An Algorithm for Synthesis of Reversible Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Test generation for combinational quantum cellular automata (QCA) circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Threshold network synthesis and optimization and its application to nanotechnologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Efficient fingerprint-based user authentication for embedded systems.
Proceedings of the 42nd Design Automation Conference, 2005
2004
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.
Proceedings of the 2004 Design, 2004
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.
Proceedings of the 2004 Design, 2004
2003
A High-level Interconnect Power Model for Design Space Exploration.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003