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1999
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.
[DOI]
Hajime Kubosawa
,
Naoshi Higaki
,
Satoshi Ando
,
Hiromasa Takahashi
,
Yoshimi Asada
,
Hideaki Anbutsu
,
Tomio Sato
,
Masato Sakate
,
Atsuhiro Suga
,
Michihide Kimura
,
Hideo Miyake
,
Hiroshi Okano
,
Akira Asato
,
Yasunori Kimura
,
Hiroshi Nakayama
,
Masayoshi Kimoto
,
Katsuji Hirochi
,
Hideki Saito
,
Norio Kaido
,
Yukihiro Nakagawa
,
Toshio Shimada
IEEE J. Solid State Circuits, 1999