CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture.
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CoRR, May, 2025
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
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IEEE J. Solid State Circuits, April, 2025
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
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CoRR, February, 2025
ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders.
CoRR, February, 2025
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
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CoRR, January, 2025
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance.
Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2025
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution.
Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.
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IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor.
CoRR, 2024
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores Through ISA-Supported Temporal Partitioning.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2024
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning.
IEEE Trans. Computers, May, 2023
Proving the Absence of Microarchitectural Timing Channels.
CoRR, 2023
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Towards a RISC-V Open Platform for Next-generation Automotive ECUs.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs.
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Proceedings of the 35th IEEE Hot Chips Symposium, 2023
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core.
CoRR, 2020