FDTNet: Enhancing frequency-aware representation for prohibited object detection from X-ray images via dual-stream transformers.
Eng. Appl. Artif. Intell., 2024
MC-DC: An MLP-CNN Based Dual-path Complementary Network for Medical Image Segmentation.
Comput. Methods Programs Biomed., December, 2023
M-CBN: Manifold constrained joint image dehazing and super-resolution based on chord boosting network.
Pattern Recognit., 2023
TMS-GAN: A Twofold Multi-Scale Generative Adversarial Network for Single Image Dehazing.
IEEE Trans. Circuits Syst. Video Technol., 2022
RAOD: refined oriented detector with augmented feature in remote sensing images object detection.
Appl. Intell., 2022
SS3: Security-Aware Vendor-Constrained Task Scheduling for Heterogeneous Multiprocessor System-on-Chips.
Proceedings of the IEEE International Conference on Networking, Sensing and Control, 2020
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis.
Integr., 2019
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems.
Integr., 2019
Weighted Domain Transfer Extreme Learning Machine and Its Online Version for Gas Sensor Drift Compensation in E-Nose Systems.
Wirel. Commun. Mob. Comput., 2018
Online Sensor Drift Compensation for E-Nose Systems Using Domain Adaptation and Extreme Learning Machine.
Sensors, 2018
Power-gating-aware scheduling with effective hardware resources optimization.
Integr., 2018
Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis.
IEEE Access, 2018
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
A Flexible Broadband Single RF Architecture Based on Time-Modulated Array.
Proceedings of the Communications, Signal Processing, and Systems, 2018
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Unified Scheduling Approach for Power and Resource Optimization With Multiple V<sub>dd</sub> or/and V<sub>th</sub> in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Tabu search based multiple voltage scheduling under both timing and resource constraints.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Primal-dual method based simultaneous functional unit and register binding.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Leakage Power Aware Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Min-cut based leakage power aware scheduling in high-level synthesis.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Mobility overlap-removal based leakage power aware scheduling in high-level synthesis.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Power and resource aware scheduling with multiple voltages.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Timing and resource constrained leakage power aware scheduling in high-level synthesis.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Interconnection allocation between functional units and registers in High-Level Synthesis.
Proceedings of the IEEE 10th International Conference on ASIC, 2013