FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and Hyperdimensional Computing.
CoRR, 2024
PatterNet: explore and exploit filter patterns for efficient deep neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design.
Proceedings of the TENCON 2018, 2018
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Bike sharing data analytics for silicon valley in USA.
Proceedings of the 2017 IEEE SmartWorld, 2017