Lucas C. Cordeiro

CoRR, 2021

Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach.

[DOI]

Ali Mustafa Zaidi

Giacomo Gabrielli

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Robust SLAM Systems: Are We There Yet?

[DOI]

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

Power and energy efficient routing for Mach-Zehnder interferometer based photonic switches.

[DOI]

Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating.

[DOI]

William B. Toms

Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021

2020

Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi.

[DOI]

Mireya Paredes

Athanasios Stratikopoulos

IEEE Trans. Parallel Distributed Syst., 2020

FastPath_MP: Low Overhead & Energy-efficient FPGA-based Storage Multi-paths.

[DOI]

Crefeda Faviola Rodrigues

ACM Trans. Archit. Code Optim., 2020

Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks.

[DOI]

Simul. Model. Pract. Theory, 2020

Toward FPGA-Based HPC: Advancing Interconnect Technologies.

[DOI]

IEEE Micro, 2020

Energy Predictive Models for Convolutional Neural Networks on Mobile Platforms.

[DOI]

CoRR, 2020

spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System.

[DOI]

IEEE Access, 2020

TruffleWasm: a WebAssembly interpreter on GraalVM.

[DOI]

Salim S. Salim

Proceedings of the VEE '20: 16th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2020

Optimising dynamic binary modification across 64-bit Arm microarchitectures.

[DOI]

Guillermo Callaghan

Proceedings of the VEE '20: 16th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2020

PMThreads: persistent memory threads harnessing versioned shadow copies.

[DOI]

Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

To Ensemble or Not Ensemble: When Does End-to-End Training Fail?

[DOI]

Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2020

Analysis of the Usage Models of System Memory Management Unit in Accelerator-attached Translation Units.

[DOI]

Kyriakos Paraskevas

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs.

[DOI]

Unai Martinez-Corral

Guillermo Callaghan

Koldo Basterretxea

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Balancing performance and productivity for the development of dynamic binary instrumentation tools: a case study on Arm systems.

[DOI]

Guillermo Callaghan

Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2019

INRFlow: An interconnection networks research flow-level simulation framework.

[DOI]

J. Parallel Distributed Comput., 2019

Lightweight Container-based User Environment.

[DOI]

CoRR, 2019

Can the Optimizer Cost be Used to Predict Query Execution Times?

[DOI]

Anthony Kleerekoper

CoRR, 2019

Joint Training of Neural Network Ensembles.

[DOI]

CoRR, 2019

On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects.

[DOI]

Concurr. Comput. Pract. Exp., 2019

Enabling shared memory communication in networks of MPSoCs.

[DOI]

Concurr. Comput. Pract. Exp., 2019

Profiling and Tracing Support for Java Applications.

[DOI]

Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

ORB-SLAM-CNN: Lessons in Adding Semantic Map Construction to Feature-Based SLAM.

[DOI]

Andrew M. Webb

Proceedings of the Towards Autonomous Robotic Systems - 20th Annual Conference, 2019

An analysis of call-site patching without strong hardware support for self-modifying-code.

[DOI]

Proceedings of the 16th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2019

Hosting OpenMP programs on Java virtual machines.

[DOI]

Swapnil Gaikwad

Proceedings of the 16th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2019

Towards a WebAssembly standalone runtime on GraalVM.

[DOI]

Salim S. Salim

Proceedings of the Proceedings Companion of the 2019 ACM SIGPLAN International Conference on Systems, 2019

Scalability analysis of optical Beneš networks based on thermally/electrically tuned Mach-Zehnder interferometers.

[DOI]

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

Scaling the capacity of memory systems; evolution and key approaches.

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

SLAMBench 3.0: Systematic Automated Reproducible Evaluation of SLAM Systems for Robot Vision Challenges and Scene Understanding.

[DOI]

Proceedings of the International Conference on Robotics and Automation, 2019

Design Exploration of Multi-tier Interconnection Networks for Exascale Systems.

[DOI]

Proceedings of the 48th International Conference on Parallel Processing, 2019

FullFusion: A Framework for Semantic Reconstruction of Dynamic Scenes.

[DOI]

Mihai Bujanca

Barry Lennox

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019

Enabling Standalone FPGA Computing.

[DOI]

Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs.

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level.

[DOI]

Nikos Foutris

Crefeda Faviola Rodrigues

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Exploration of task-based scheduling for convolutional neural networks accelerators under memory constraints.

[DOI]

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Receive-Side Notification for Enhanced RDMA in FPGA Based Networks.

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

POSTER: Quiescent and Versioned Shadow Copies for NVM.

[DOI]

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

POSTER: Runtime Adaptations for Energy-Efficient VSLAM.

[DOI]

Abdullah Khalufa

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Cross-Language Interoperability in a Multi-Language Runtime.

[DOI]

ACM Trans. Program. Lang. Syst., 2018

Type Information Elimination from Objects on Architectures with Tagged Pointers Support.

[DOI]

IEEE Trans. Computers, 2018

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.

[DOI]

Proc. IEEE, 2018

Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.

[DOI]

Pier Stanislao Paolucci

Microprocess. Microsystems, 2018

A Survey on Optical Network-on-Chip Architectures.

[DOI]

ACM Comput. Surv., 2018

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.

[DOI]

CoRR, 2018

Optimising Dynamic Binary Modification Across ARM Microarchitectures.

[DOI]

Amanieu D'Antras

Proceedings of the 2018 ACM/SPEC International Conference on Performance Engineering, 2018

Performance analysis for languages hosted on the truffle framework.

[DOI]

Swapnil Gaikwad

Proceedings of the 15th International Conference on Managed Languages & Runtimes, 2018

Exploiting high-performance heterogeneous hardware for Java programs using graal.

[DOI]

James Clarkson

Juan Fumero

Michail Papadimitriou

Proceedings of the 15th International Conference on Managed Languages & Runtimes, 2018

SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM.

[DOI]

Athanasios Stratikopoulos

Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

FastPath: Towards Wire-Speed NVMe SSDs.

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A CAM-Free Exascalable HPC Router for Low-Energy Communications.

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017

Fine-grained checkpoint based on non-volatile memory.

[DOI]

Frontiers Inf. Technol. Electron. Eng., 2017

Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip.

[DOI]

Crefeda Faviola Rodrigues

JOCN, 2017

Dealing with under-reported variables: An information theoretic solution.

[DOI]

Konstantinos Sechidis

Int. J. Approx. Reason., 2017

Flexible Page-level Memory Access Monitoring Based on Virtualization Hardware.

[DOI]

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Heterogeneous Managed Runtime Systems: A Computer Vision Case Study.

[DOI]

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation.

[DOI]

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Experiences with Building Domain-Specific Compilation Plugins in Graal.

[DOI]

Proceedings of the 14th International Conference on Managed Languages and Runtimes, 2017

Low overhead dynamic binary translation on ARM.

[DOI]

Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2017

MaxSim: A simulation platform for managed applications.

[DOI]

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Fine-grained energy profiling for deep convolutional neural networks on the Jetson TX1.

[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

ACTiCLOUD: Enabling the Next Generation of Cloud Applications.

[DOI]

Proceedings of the 37th IEEE International Conference on Distributed Computing Systems, 2017

Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links.

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Subchannel Scheduling for Shared Optical On-chip Buses.

[DOI]

Proceedings of the 25th IEEE Annual Symposium on High-Performance Interconnects, 2017

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation.

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

The Next Generation of Exascale-Class Systems: The ExaNeSt Project.

[DOI]

Pier Stanislao Paolucci

Proceedings of the Euromicro Conference on Digital System Design, 2017

Vectorization of Hybrid Breadth First Search on the Intel Xeon Phi.

[DOI]

Mireya Paredes

Proceedings of the Computing Frontiers Conference, 2017

Designing an exascale interconnect using multi-objective optimization.

[DOI]

Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

Boosting Java Performance Using GPGPUs.

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016

Compiler-Driven Software Speculation for Thread-Level Parallelism.

[DOI]

Paraskevas Yiapanis

ACM Trans. Program. Lang. Syst., 2016

MAMBO: A Low-Overhead Dynamic Binary Modification Tool for ARM.

[DOI]

Amanieu D'Antras

ACM Trans. Archit. Code Optim., 2016

Optimizing Indirect Branches in Dynamic Binary Translators.

[DOI]

ACM Trans. Archit. Code Optim., 2016

Purge-Rehab: Eager Software Transactional Memory with High Performance Under Contention.

[DOI]

Abubakar Siddique

Mohammad Ansari

Int. J. Parallel Program., 2016

Integrating Transactions into the Data-Driven Multi-threading Model Using the TFlux Platform.

[DOI]

Int. J. Parallel Program., 2016

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip.

[DOI]

ACM Comput. Surv., 2016

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling.

[DOI]

IEEE Comput. Archit. Lett., 2016

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

HAPPY: Hybrid Address-based Page Policy in DRAMs.

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

A partial reconfiguration controller for Altera Stratix V FPGAs.

[DOI]

Zhenzhong Xiao

Dirk Koch

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Parallel Hardware Merge Sorter.

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Breadth first search vectorization on the Intel Xeon Phi.

[DOI]

Mireya Paredes

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Towards co-designed optimizations in parallel frameworks: a MapReduce case study.

[DOI]

Colin Barrett

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding.

[DOI]

Govind Sreekar Shenoy

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.

[DOI]

J. Supercomput., 2015

Write-Combined Logging: An Optimized Logging for Consistency in NVRAM.

[DOI]

Sci. Program., 2015

SpiNNaker: Enhanced multicast routing.

[DOI]

Parallel Comput., 2015

Objective Assessment of Asthenia using Energy and Low-to-High Spectral Ratio.

[DOI]

Farideh Jalalinajafabadi

Proceedings of the SIGMAP 2015, 2015

Analysis of FPGA and software approaches to simulate unconventional computer architectures.

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

CHO: towards a benchmark suite for OpenCL FPGA accelerators.

[DOI]

Geoffrey Ndu

Proceedings of the 3rd International Workshop on OpenCL, 2015

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM.

[DOI]

Nigel P. Topham

Stephen B. Furber

Proceedings of the IEEE International Conference on Robotics and Automation, 2015

Amon: An Advanced Mesh-like Optical NoC.

[DOI]

Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Effective Barrier Synchronization on Intel Xeon Phi Coprocessor.

[DOI]

Proceedings of the Euro-Par 2015: Parallel Processing, 2015

Computerised objective measurement of strain in voiced speech.

[DOI]

Farideh Jalalinajafabadi

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

A scalable implementation of information theoretic feature selection for high dimensional data.

[DOI]

Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

2014

TERAFLUX: Harnessing dataflow in next generation teradevices.

[DOI]

Microprocess. Microsystems, 2014

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

On generating multicast routes for SpiNNaker.

[DOI]

Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013

Optimizing software runtime systems for speculative parallelization.

[DOI]

ACM Trans. Archit. Code Optim., 2013

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.

[DOI]

Parallel Comput., 2013

Software transactional memories for Scala.

[DOI]

J. Parallel Distributed Comput., 2013

A Flexible Memory Controller Supporting Deep Belief Networks with Fixed-Point Arithmetic.

[DOI]

Jingfei Jiang

Rongdong Hu

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Effect of fixed-point arithmetic on deep belief networks (abstract only).

[DOI]

Jingfei Jiang

Rongdong Hu

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Perceptual Evaluation of Voice Quality and Its Correlation with Acoustic Measurement.

[DOI]

Farideh Jalalinajafabadi

Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices.

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Exploring sketches for probability estimation with sublinear memory.

[DOI]

Anthony Kleerekoper

Proceedings of the 2013 IEEE International Conference on Big Data (IEEE BigData 2013), 2013

Empirical Evaluation of Fixed-Point Arithmetic for Deep Belief Networks.

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Informative Priors for Markov Blanket Discovery.

[DOI]

Adam Craig Pocock

Dionisios N. Pnevmatikatos

Proceedings of the Fifteenth International Conference on Artificial Intelligence and Statistics, 2012

Conditional Likelihood Maximisation: A Unifying Framework for Information Theoretic Feature Selection.

[DOI]

J. Mach. Learn. Res., 2012

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.

[DOI]

Int. J. Parallel Program., 2012

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Architectural Support for Exploiting Fine Grain Parallelism.

[DOI]

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.

[DOI]

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Transactional Access to Shared Memory in StarSs, a Task Based Programming Model.

[DOI]

Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Topic 11: Multicore and Manycore Programming.

[DOI]

Eduard Ayguadé

Rudolf Eigenmann

Sabri Pllana

Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection.

[DOI]

Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011

Transaction Reordering to Reduce Aborts in Software Transactional Memory.

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2011

Robust Adaptation to Available Parallelism in Transactional Memory Applications.

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2011

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.

[DOI]

Parallel Comput., 2011

Garbage collection auto-tuning for Java mapreduce on multi-cores.

[DOI]

Proceedings of the 10th International Symposium on Memory Management, 2011

2010

Modeling Spiking Neural Networks on SpiNNaker.

[DOI]

Comput. Sci. Eng., 2010

Online Non-stationary Boosting.

[DOI]

Proceedings of the Multiple Classifier Systems, 9th International Workshop, 2010

The economics of garbage collection.

[DOI]

Proceedings of the 9th International Symposium on Memory Management, 2010

Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.

[DOI]

Xin Jin

Muhammad Mukaram Khan

Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010

Clustering JVMs with software transactional memory support.

[DOI]

Mohammad Ansari

Konstantinos Malakasis

Behram Khan

Chris C. Kirkham

Ian Watson

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Toward a more accurate understanding of the limits of the TLS execution paradigm.

[DOI]

Nikolas Ioannou

Jeremy Singer

Salman Khan

Polychronis Xekalakis

Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Improving Performance by Reducing Aborts in Hardware Transactional Memory.

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Scalable Object-Aware Hardware Transactional Memory.

[DOI]

Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

Fundamental Nano-Patterns to Characterize and Classify Java Methods.

[DOI]

Proceedings of the Ninth Workshop on Language Descriptions Tools and Applications, 2009

Exploiting object structure in hardware transactional memory.

Comput. Syst. Sci. Eng., 2009

Profiling Transactional Memory Applications.

[DOI]

Proceedings of the 17th Euromicro International Conference on Parallel, 2009

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.

[DOI]

Muhammad Mukaram Khan

Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

On the Performance of Contention Managers for Complex Transactional Memory Benchmarks.

[DOI]

Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Understanding the interconnection network of SpiNNaker.

[DOI]

Proceedings of the 23rd international conference on Supercomputing, 2009

Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008

A first insight into object-aware hardware transactional memory.

[DOI]

Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

Experiences using adaptive concurrency in transactional memory with Lee's routing algorithm.

[DOI]

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Investigating software Transactional Memory on clusters.

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

DiSTM: A Software Transactional Memory Framework for Clusters.

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

Adaptive Loop Tiling for a Multi-cluster CMP.

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

Introducing Aspects to the Implementation of a Java Fork/Join Framework.

[DOI]

Chrysoulis Zambas

Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory.

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

An Object-Aware Hardware Transactional Memory System.

[DOI]

Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008

Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate.

[DOI]

Proceedings of the Euro-Par 2008, 2008

2007

Towards intelligent analysis techniques for object pretenuring.

[DOI]

Proceedings of the 5th International Symposium on Principles and Practice of Programming in Java, 2007

Adaptive performance control for distributed scientific coupled models.

[DOI]

Mohamed Khamiss Hussein

Kenneth R. Mayes

John R. Gurd

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

Speculative Parallelization - Eliminating the Overhead of Failure.

[DOI]

Proceedings of the High Performance Computing and Communications, 2007

A Study of a Transactional Parallel Routing Algorithm.

[DOI]

Ian Watson

Chris C. Kirkham

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Performance Evaluation of Storage Formats for Sparse Matrices in Fortran.

[DOI]

Proceedings of the High Performance Computing and Communications, 2006

2005

Elimination of Java array bounds checks in the presence of indirection.

[DOI]

Concurr. Pract. Exp., 2005

On the conditions necessary for removing abstraction penalties in OOLALA.

[DOI]

T. L. Freeman

John R. Gurd

Concurr. Pract. Exp., 2005

Performance control of scientific coupled models in Grid environments.

[DOI]

Christopher W. Armstrong

Concurr. Pract. Exp., 2005

DIFOJO: A Java Fork/Join Framework for Heterogeneous Networks.

[DOI]

Proceedings of the 13th Euromicro Workshop on Parallel, 2005

Storage Formats for Sparse Matrices in Java.

[DOI]

Proceedings of the Computational Science, 2005

2000

OoLALA: an object oriented analysis and design of numerical linear algebra.

[DOI]

T. L. Freeman

John R. Gurd

Proceedings of the 2000 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 2000

Building an object oriented problem solving environment for the parallel numerical solution of PDEs.

[DOI]