A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
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Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.
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Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array.
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IEEE J. Solid State Circuits, 2008