2024
UnCLe: Unsupervised Continual Learning of Depth Completion.
CoRR, 2024
2023
Automated Detection of Under-Constrained Circuits in Zero-Knowledge Proofs.
Proc. ACM Program. Lang., 2023
Automated Detection of Underconstrained Circuits for Zero-Knowledge Proofs.
IACR Cryptol. ePrint Arch., 2023
2019
Respiration rate and volume measurements using wearable strain sensors.
npj Digit. Medicine, 2019
2015
High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology.
Proc. IEEE, 2015
2014
Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Design of BiCMOS SRAMs for high-speed SiGe applications.
IET Circuits Devices Syst., 2014
2011
Carry Chains for Ultra High-Speed SiGe HBT Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications.
IET Circuits Devices Syst., 2011
2010
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology".
IEEE J. Solid State Circuits, 2010
A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2010
2009
Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.
Proc. IEEE, 2009
Scientific and Engineering Computing Using ATI Stream Technology.
Comput. Sci. Eng., 2009
Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers.
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Proceedings of the IEEE International Conference on 3D System Integration, 2009
2007
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007
52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology.
IET Circuits Devices Syst., 2007
Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
Stream computations organized for reconfigurable execution.
Microprocess. Microsystems, 2006
Hybrid transactional memory.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006
2005
A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block.
Microprocess. Microsystems, 2005
A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.
Integr., 2005
A High Speed Reconfigurable Gate Array for Gigahertz Applications.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
A 11 GHz FPGA with Test Applications.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
The gigahertz FPGA: design consideration and applications.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
2003
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
2002
Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002
2001
DataSplash: A Direct Manipulation Environment for Programming Semantic Zoom Visualizations of Tabular Data.
J. Vis. Lang. Comput., 2001
2000
Stream Computations Organized for Reconfigurable Execution (SCORE).
Proceedings of the Field-Programmable Logic and Applications, 2000
1998
Proceedings of the SIGMOD 1998, 1998
Object Oriented Circuit-Generators in Java.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability.
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Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998