A 12.1 TOPS/W Mixed-precision Quantized Deep Convolutional Neural Network Accelerator for Low Power on Edge / Endpoint Device.
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Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
Design and Implementation of the Loop Restructuring Feature for the MIRAI Parallelizing Complier.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003
An Automatic Parallelizing Compiler MIRAI with Data Distribution Function and its Runtime Support System Fagus for Distributed Memory Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002